1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more specifically it relates to a semiconductor device in which a diffusion layer and an element separation insulation film are formed in a self-aligning manner, and to a method for manufacturing such as semiconductor device.
2. Description of the Related Art
In the past, with respect to a method for manufacturing a non-volatile semiconductor memory device such as a flash memory, there have been many disclosures of known technologies.
For example, one example of a method for manufacturing a flash memory in the past was disclosed in the Japanese Unexamined Patent Publication (KOKAI)No. 6-283721, the technological purport of which will be described with reference to FIG. 12 (A) through FIG. 12(G).
Specifically, in this method of the past, as shown in FIG. 12(A), a known lithographic method is first used to form the element separations 201 and 202, after which, as shown in FIG. 12(B), a silicon oxide film 203, which will serve as a tunnel film, is formed.
Next, as shown in FIG. 12(C), polysilicon 204, which will serve as a floating gate, and an ONO film 205, which will serve as a capacitive film between the control gate and floating gate are formed, after which, as shown in FIG. 12(D), lithography is used to pattern the ONO film 205 and the polysilicon 204, and ion implantation is used to form the source and drain 213 and 214.
Additionally, as shown in FIG. 12(E), the drain side only is covered by a mash, and the source is subjected to ion implantation, so as to impart to the source a structure with a high withstand voltage.
Finally, as shown in FIG. 12(E), resist is removed and, after oxidizing the diffusion layer and the side surface of the floating gate 204, as shown in FIG. 12(G) polysilicon 219, which will serve as the control gate, is formed, patterning being done of the control gate 219, the ONO film 205, and the floating gate 204, in this sequence, so as to form the memory cell.
In the method for manufacturing a non-volatile semiconductor memory device of the past, however, because the channel region and the element separation region are formed by separate lithography process steps, skew of position in the lithography process can cause a change in width of the channel region and element separation region, the result being non-uniformity in the characteristics of the memory cells.
For this reason, it is necessary to provide a sufficient diffusion layer width with respect to this variation, the result being the problem that the size of the memory cell increases.
In the Japanese Unexamined Patent Publication (KOKAI)No. 7-142618, there is disclosure of a method of forming a source region, and drain region, and an element separation region that are each self-aligning.
However, this method involves complex film growing processes, the number of process steps being large, and the cost being high, in addition to the problem that it is difficult to make the size of each individual transistor small.
Accordingly, it is an object of the present invention to improve on the above-noted drawbacks of the prior, by providing a semiconductor device in which the channel region, diffusion layer region, and element separation region of a transistor element are all established by one lithography step, the widths of each of these regions being thereby uniquely established, thereby enabling the suppression of non-uniformity in the characteristics of the memory cells and enabling the size of the transistor elements to be made small.
A further object of the present invention is to provide a method for manufacturing the above-noted semiconductor device.